Verification is an important step in the process of designing and creating an electronic product. Verification helps ensure that the electronic design will work for its intended purpose, and is usually performed at several stages of the electronic design process. Circuit designers and verification engineers use different methods and analysis tools to verify circuit designs, including simulation. Simulation verifies a design by monitoring computed behaviors of the design with respect to test stimuli. A variety of commercially offered software programs are available for circuit simulation.
Circuit performance measurements may be undertaken by a simulator or a post-simulation engine that evaluates stored simulated circuit waveforms. Simulator output is often saved in binary and text form for such analysis. Circuit operations may be verified during simulation by evaluating assertions, which are statements that are intended to always be true during correct circuit behavior. Assertions are commonly used to monitor the simulated operating conditions of individual semiconductor devices or other circuit components. Violations of such assertions may for example indicate that the monitored device has been exposed to conditions during simulation that exceed its maximum safe ratings.
Analysis of so-called “safe operating area” (SOA) assertions is therefore a required step in a circuit design flow. To validate the circuit design, designers must verify that devices do not encounter dangerous operating conditions that may result in reliability issues and product failures. As technologies advance, more numerous and complex SOA checks have been implemented, often as assertions, so that simulating even a relatively small circuit block may produce hundreds of assertion violations.
However, not all of these SOA violations are related to a really dangerous situation. Some assertions may just trigger routine warning messages, while others may denote more serious risk to the circuit depending on the cumulative duration of the violations. For example, many devices may safely sustain a relatively high voltage for a very short time, but not for longer times.
Designers must therefore expend considerable effort to investigate all of the assertion violations to locate and act on the more serious ones. This requirement leads to several negative consequences, including increased design time, and an increased chance of error. Some errors may result in an overdesign scenario (if a “false alarm” is mistaken for a real issue), while others may result in a product failure (if a serious violation is ignored). The circuit design community therefore needs a tool that enables designers to filter assertion violation messages, to easily determine which assertion violations are really dangerous.
Accordingly, the inventors have developed a novel way to help circuit designers manage SOA assertion violations and related simulation output.